ISL12032IVZ【PDF 9/26 页】IC RTC LP BATT BACK SRAM 14TSSOP

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FN6618.3

May 5, 2011

Where the ROUT is the selected resistor between VDD and

VBAT. Table 14 gives the typical resistor values for VDD = 5V

and VBAT = 3.0V. Note that the resistor value changes with

VDD input voltage and VBAT voltage, as well as with

temperature.

Power Supply Control Register (PWRVDD)

CLEAR TIME STAMP BIT (CLRTS)

This bit clears both the Time Stamp VDD to Battery (TSV2B)

and Time Stamp Battery to VDD (TSB2V) sections. The

default setting is “0” which allows normal operation. Setting

CLRTS = 1 performs the clear timestamp register function at

the conclusion of a successful write operation.

I2C IN BATTERY MODE (I2CBAT)

This bit allows I2C operation in battery backup mode (VBAT

powered) when set to “1”. When reset to “0”, the I2C

operation is disabled in battery mode, which results in the

lowest IDD current.

Note that when the I2C operation is desired in VBAT mode,

the SCL and SDA pull-ups must go to the VBAT source for

proper communications. This will result in additional VBAT

current drain (on top of the increased device VBAT current)

during serial communications.

VDD BROWNOUT TRIP VOLTAGE (VDDTRIP <2:0>)

These bits set the 6 trip levels for the VDD alarm and VBAT

switchover. The LVDD bit in the SRDC is set to “1” when

VDD drops below this preset level. See Table 16.

Battery Voltage Warning Register (PWRVBAT)

This register controls the trip points for the two VBAT

warnings, with levels set to approximately 85% and 75% of

the nominal battery level.

VBAT HYSTERESIS (BHYS)

This bit enables/disables the hysteresis voltage for the

VDD/VBAT switchover. When set to “1”, hysteresis is enabled

and switching to VBAT occurs at approximately 50mV below

the VDD Trip point (set by VDDTrip<2:0>). Switching from

VBAT to VDD power will occur at approximately 50mV above

the VDD trip point.

When set to “0”, there is no hysteresis and switchover will

occur at exactly the VDD trip point. Note that for slow moving

VDD power-down and power-up signals there can be some

extra switching cycles without hysteresis.

BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>)

Three bits selects the first alarm (85% of Nominal VBAT) level

for the battery voltage monitor. There are total of 7 levels that

could be selected for the first warning. Any of the levels could

be selected as the first warning with no reference as to nominal

VBAT voltage level. See Table 18 for typical values.

TABLE 14. RESISTOR SELECTION REGISTER

TRKRO1

TRKRO0

Rtrk

UNITS

1300

2200

3600

7800

TABLE 15. POWER SUPPLY CONTROL REGISTER (PWRVDD)

ADDR

11h

CLRTS

I2CBAT

LVENB

VDD

Trip2

VDD

Trip1

VDD

Trip0

TABLE 16. VDD TRIP LEVELS

VDDTrip2

VDDTrip1

VDDTrip0

TRIP

VOLTAGE

(V)

2.295

2.550

2.805

MAX

BAT

–

OUT

---------------------------------

(EQ. 1)

3.060

4.250

4.675

TABLE 17. BATTERY VOLTAGE WARNING REGISTER

(PWRVBAT)

ADDR

12h

X BHYS VB85T

VB85T

VB75T

TABLE 16. VDD TRIP LEVELS

VDDTrip2

VDDTrip1

VDDTrip0

TRIP

VOLTAGE

(V)

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